Building an SDMMC HAL - Part 2 of N: 2025-08-26

SDIO on the ESP32-C6

Continuing from where we left off, development has progressed on writing an SDIO driver for the ESP32-C6 SoC.

esp-hal tests

After writing enough code to tie into the rest of esp-hal, it is finally ready to write some initial integrations tests on real hardware.

For these integration tests, we’ll be using the ESP32-C6-DevKitC-1 development board, technically two of them.

Originally, it seemed that the driver could be tested on a single board. After all, the SoC has both a SPI host, and the SDIO device supports SPI mode. No problem, right?

Wrong. According to the SDIO spec, commands and responses are transferred on the CMD line. In SPI mode, this is the MOSI line. So, the SPI host would need to write to the CMD line, while the SDIO device simultaneously reads from the CMD line. The only way to reasonably achieve this would be to run the test progam as two separate halves: one on the high-power core, and one on the low-power core. This may still be feasible, but is not the direction I’m choosing.

For detailed instructions that include pinout diagrams, the SDIO Card Slave Driver is a good reference. It’s based on the esp-idf, but still has enough general information to be useful for our purposes in esp-hal.

Looking around the test suite to see if there would be any help from other SPI tests, and found some inspiration taken from the spi_slave. In this test, a bitbanged SPI host makes transfers with an SPI device using DMA. Unfortunately, since we are focusing on the CMD/RESPONSE flow of the SDIO protocol, we won’t be using the SDIO-dedicated DMA (it’s only used for DATA transfers). However, the bitbanged SPI host may prove useful.

So, if the HIL-test won’t work without some very involved hacks, what to do?

After some discussion with @bugadani (many thanks), it seems like the qa-test module may be a better fit for splitting the integration test into two parts, and manually flashing the tests to the devices.

Test setup

One half of the test controls the SPI host communication. Initially, this is instantiated as a normal spi::master::Spi driver, though it’s looking like a bitbanged SPI driver will probably be necessary.

Regardless, there are now some starting points for qa-test binaries:

• qa-test/src/bin/sdio-spi-device.rs
• qa-test/src/bin/sdio-spi-host.rs

The tests can be built using cargo-xtask from the project root:

$ cargo xtask build examples --package qa-test --chip esp32c6 sdio-spi-device
$ cargo xtask build examples --package qa-test --chip esp32c6 sdio-spi-host

Afterwards, the binaries can be flashed to the device using probe-rs:

// Connect the `device`-side ESP32-C6 via the JTAG USB-C port
$ probe-rs flash --probe 303a:1001 --chip esp32c6 qa-test/target/riscv32imac-unknown-none-elf/release/sdio-spi-device

// Connect the `host`-side ESP32-C6 via the JTAG USB-C port
$ probe-rs flash --probe 303a:1001 --chip esp32c6 qa-test/target/riscv32imac-unknown-none-elf/release/sdio-spi-host

It is also possible to connect a GDB debug server, and connect a riscv32 GDB:

// Connect a GDB debugger to the `device`-side ESP32-C6 via the JTAG USB-C port
$ probe-rs gdb --gdb /path/to/riscv32-unknown-linux-gnu-gdb --probe 303a:1001 --chip esp32c6 qa-test/target/riscv32imac-unknown-none-elf/release/sdio-spi-device

// Connect a GDB debugger to the `host`-side ESP32-C6 via the JTAG USB-C port
$ probe-rs gdb --gdb /path/to/riscv32-unknown-linux-gnu-gdb --probe 303a:1001 --chip esp32c6 qa-test/target/riscv32imac-unknown-none-elf/release/sdio-spi-host

NOTE: if you connect both dev boards simultaneously, you will need the full serial in the --probe argument.

NOTE: use probe-rs info to get the full serial number of each device

Test results

Getting the GDB debugger connected is about as far as we’ve reached, so far. Even setting breakpoints at the expected main function doesn’t seem to work properly. Don’t know, probably holding the debugger wrong, or something...

There may also be some incorrect wiring, so will need to double check eveything gets wired together properly.

Wiring

Here are some pictures of the current bench setup.

ESP32-C6-DevKitC-1 development boards wired for SDIO in SPI mode tests. Left: SPI host, Right: SDIO device

ESP32-C6-DevKitC-1 SDIO device close-up

ESP32-C6-DevKitC-1 SPI host close-up